With synchronization circuits, generally, a clock tree is used for the purpose of distributing a common clock signal with uniform timing to many flip-flops. An H tree structure or mesh tree structure or the like is widely used as the clock tree structure (refer to “Clock Distribution Networks in Synchronous Digital Integrated Circuits,” Proceedings of the IEEE, US, IEEE May 2001, Vol. 89, No. 5, pp. 665-692.
With an H tree structure, clock buffers are arranged symmetrically so that the wiring that connects each level of the tree is in an H-type symmetrical shape. Wiring lengths from the tree starting point to the flip-flops are approximately equal because of this, and there is little skew in the clock signal.
With a mesh structure, wiring in a symmetrical mesh form is formed on a semiconductor chip. Clock buffer inputs at the clock tree termini are connected symmetrically to some of the points of intersection of the mesh wiring. Clock buffer outputs one level before the clock tree termini are connected to other points of intersection of the mesh wiring to be symmetrical for each input of the clock buffers at the clock tree termini. By using such a structure, wiring lengths from the tree starting point to the flip-flops are approximately equal, and variation in clock buffer drive capability is equalized, so skew is even smaller.
The H tree structure and mesh structure described above are primarily used in fast circuits. With large-scale LSls, a technique called CTS (clock tree synthesis) to automatically synthesize a clock tree with an EDA tool is generally used.
However, because the layout of flip-flops on a circuit board is essentially irregular, in a large-scale LSl in particular, it is difficult to apply a clock tree with a symmetrical structure, such as an H tree structure or mesh structure. With a technique where the clock tree arrangement is fixed in advance, because significant restrictions are applied to the flip-flop arrangement, layout design automation is difficult, and in large-scale LSl design, the disadvantage is that layout requires a large amount of time.
On the other hand, with a technique where a clock tree is synthesized automatically with an EDA tool, there is a tendency for many buffers to be inserted to satisfy requirements such as skew or load capacitance. For this reason, there are disadvantages, i.e., power consumption is greater and clock signal delay increases. And because variation occurs in buffer characteristics even on the same chip, there is the disadvantage that as the number of buffers increase, clock signal timing variation increases.